GICV3中断控制器调用流程

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GICV3中断控制器初始化调用链

1. /kernel/irq/handle.c:
2. #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
3. int __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
4. {
5.     if (handle_arch_irq)
6.         return -EBUSY;
8.     handle_arch_irq = handle_irq;
9.     return 0;
10. }
11. #endif

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1. /drivers/irqchip/irq-gic-v3.c:
2. static int __init gic_init_bases(void __iomem *dist_base,
3.                  struct redist_region *rdist_regs,
4.                  u32 nr_redist_regions,
5.                  u64 redist_stride,
6.                  struct fwnode_handle *handle)
7. {
8. ... ...
9.     set_handle_irq(gic_handle_irq);
10. ... ...
11. }

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1. /drivers/irqchip/irq-gic-v3.c:
3. IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
5. static int __init gic_of_init(struct device_node *node, struct device_node *parent)
6. {
7. ... ...
8.     err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
9.                  redist_stride, &node->fwnode);
10. ... ....
11. }

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1. /include/linux/irqchip.h:
2. #define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn)
4. /include/linux/of.h:
5. #define OF_DECLARE_2(table, name, compat, fn) \
6.         _OF_DECLARE(table, name, compat, fn, of_init_fn_2)
7.         
8. #define _OF_DECLARE(table, name, compat, fn, fn_type)            \
9.     static const struct of_device_id __of_table_##name        \
10.         __used __section(__##table##_of_table)            \
11.          = { .compatible = compat,                \
12.              .data = (fn == (fn_type)NULL) ? fn : fn  }

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1. /arch/arm64/kernel/vmlinux.lds:
2. .init.data : {
3. ... ...
4. . = ALIGN(8); __irqchip_of_table = .; KEEP(*(__irqchip_of_table)) KEEP(*(__irqchip_of_table_end)) . = ALIGN(8);
5. ... ...
6. }

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1. /drivers/irqchip/irqchip.c:
3. void __init irqchip_init(void)
4. {
5.     of_irq_init(__irqchip_of_table);
6.     acpi_probe_device_table(irqchip);
7. }

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1. /arch/arm64/kernel/irq.c:
2. void __init init_IRQ(void)
3. {
4.     init_irq_stacks();
5.     irqchip_init();
6. ... ...
7. }

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1. asmlinkage __visible void __init start_kernel(void)
2. {
3. ... ...
4. init_IRQ();
5. ... ...
6. }

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中断的处理过程

异常向量表vectors

1. /arch/arm64/kernel/entry.S:
2. ENTRY(vectors)
3.     kernel_ventry    1, sync_invalid            // Synchronous EL1t
4.     kernel_ventry    1, irq_invalid            // IRQ EL1t
5.     kernel_ventry    1, fiq_invalid            // FIQ EL1t
6.     kernel_ventry    1, error_invalid        // Error EL1t
8.     kernel_ventry    1, sync                // Synchronous EL1h
9.     kernel_ventry    1, irq                // IRQ EL1h
10.     kernel_ventry    1, fiq_invalid            // FIQ EL1h
11.     kernel_ventry    1, error            // Error EL1h
13.     kernel_ventry    0, sync                // Synchronous 64-bit EL0
14.     kernel_ventry    0, irq                // IRQ 64-bit EL0
15.     kernel_ventry    0, fiq_invalid            // FIQ 64-bit EL0
16.     kernel_ventry    0, error            // Error 64-bit EL0
18. #ifdef CONFIG_COMPAT
19.     kernel_ventry    0, sync_compat, 32        // Synchronous 32-bit EL0
20.     kernel_ventry    0, irq_compat, 32        // IRQ 32-bit EL0
21.     kernel_ventry    0, fiq_invalid_compat, 32    // FIQ 32-bit EL0
22.     kernel_ventry    0, error_compat, 32        // Error 32-bit EL0
23. #else
24.     kernel_ventry    0, sync_invalid, 32        // Synchronous 32-bit EL0
25.     kernel_ventry    0, irq_invalid, 32        // IRQ 32-bit EL0
26.     kernel_ventry    0, fiq_invalid, 32        // FIQ 32-bit EL0
27.     kernel_ventry    0, error_invalid, 32        // Error 32-bit EL0
28. #endif
29. END(vectors)

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el1_irq

1. /arch/arm64/kernel/entry.S:
2.     .align    6
3. el1_irq:
4.     kernel_entry 1
5.     gic_prio_irq_setup pmr=x20, tmp=x1
6.     enable_da_f
8. #ifdef CONFIG_ARM64_PSEUDO_NMI
9.     test_irqs_unmasked    res=x0, pmr=x20
10.     cbz    x0, 1f
11.     bl    asm_nmi_enter
12. 1:
13. #endif
15. #ifdef CONFIG_TRACE_IRQFLAGS
16.     bl    trace_hardirqs_off
17. #endif
19.     irq_handler
21. #ifdef CONFIG_PREEMPT
22.     ldr    x24, [tsk, #TSK_TI_PREEMPT]    // get preempt count
23. alternative_if ARM64_HAS_IRQ_PRIO_MASKING
24.     /*
25.      * DA_F were cleared at start of handling. If anything is set in DAIF,
26.      * we come back from an NMI, so skip preemption
27.      */
28.     mrs    x0, daif
29.     orr    x24, x24, x0
30. alternative_else_nop_endif
31.     cbnz    x24, 1f                // preempt count != 0 || NMI return path
32.     bl    arm64_preempt_schedule_irq    // irq en/disable is done inside
33. 1:
34. #endif
36. #ifdef CONFIG_ARM64_PSEUDO_NMI
37.     /*
38.      * When using IRQ priority masking, we can get spurious interrupts while
39.      * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a
40.      * section with interrupts disabled. Skip tracing in those cases.
41.      */
42.     test_irqs_unmasked    res=x0, pmr=x20
43.     cbz    x0, 1f
44.     bl    asm_nmi_exit
45. 1:
46. #endif
48. #ifdef CONFIG_TRACE_IRQFLAGS
49. #ifdef CONFIG_ARM64_PSEUDO_NMI
50.     test_irqs_unmasked    res=x0, pmr=x20
51.     cbnz    x0, 1f
52. #endif
53.     bl    trace_hardirqs_on
54. 1:
55. #endif
57.     kernel_exit 1
58. ENDPROC(el1_irq)

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el0_irq

1.     .align    6
2. el0_irq:
3.     kernel_entry 0
4. el0_irq_naked:
5.     gic_prio_irq_setup pmr=x20, tmp=x0
6.     ct_user_exit_irqoff
7.     enable_da_f
9. #ifdef CONFIG_TRACE_IRQFLAGS
10.     bl    trace_hardirqs_off
11. #endif
13. #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
14.     tbz    x22, #55, 1f
15.     bl    do_el0_irq_bp_hardening
16. 1:
17. #endif
18.     irq_handler
20. #ifdef CONFIG_TRACE_IRQFLAGS
21.     bl    trace_hardirqs_on
22. #endif
23.     b    ret_to_user
24. ENDPROC(el0_irq)

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irq_handler

1. /arch/arm64/kernel/entry.S:
2. /*
3. * Interrupt handling.
4. */
5.     .macro    irq_handler
6.     ldr_l    x1, handle_arch_irq
7.     mov    x0, sp
8.     irq_stack_entry
9.     blr    x1
10.     irq_stack_exit
11.     .endm

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gic_handle_irq

1. /drivers/irqchip/irq-gic-v3.c:
2. static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
3. {
4.     u32 irqnr;
6.     irqnr = gic_read_iar();
7. ... ...
9.     /* Check for special IDs first */
10.     if ((irqnr >= 1020 && irqnr <= 1023))
11.         return;
13.     /* Treat anything but SGIs in a uniform way */
14.     if (likely(irqnr > 15)) {
15. ... ...
16.         err = handle_domain_irq(gic_data.domain, irqnr, regs);
17. ... ...
18.     }
19.     if (irqnr < 16) {
20.         gic_write_eoir(irqnr);
21.         if (static_branch_likely(&supports_deactivate_key))
22.             gic_write_dir(irqnr);
23. #ifdef CONFIG_SMP
24.         /*
25.          * Unlike GICv2, we don't need an smp_rmb() here.
26.          * The control dependency from gic_read_iar to
27.          * the ISB in gic_write_eoir is enough to ensure
28.          * that any shared data read by handle_IPI will
29.          * be read after the ACK.
30.          */
31.         handle_IPI(irqnr, regs);
32. #else
33.         WARN_ONCE(true, "Unexpected SGI received!\n");
34. #endif
35.     }
36. }

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中断状态

• 硬件触发中断信号，中断assert，GIC标记中断为PENDING状态。
  
• GIC中distributor选择优先级最高的PENDING中断，发送给CPU interface, CPU interface对优先级进行判定，然后GIC发送中断请求信号给CPU, CPU进入中断异常后，通过GICC_IAR读取硬中断号，中断进入ACTIVE状态。
  
• 硬件触发新的中断信号，中断assert, GIC标记中断为ACTIVE_AND_PENDING状态
  
• CPU完成中断处理，发送EIO信号到GIC(写EOIR寄存器)
  

需要注意的是，INACTIVE PENDING ACTIVE ACTIVE_AND_PENDING，在此例中均属于GIC硬件所标记的中断状态，另外当GIC中断信号处于PENDING状态时，硬件外设无法发送新的中断信号给GIC中断控制器。事实上中断属异步通知并且没有排队的概念。

来源:https://www.cnblogs.com/forwards/p/18310037
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